1. Field of the Invention
The present invention is related to a liquid crystal display device, and more particularly, to a double-gate liquid crystal display device.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, small size and low power consumption, have gradually replaced traditional cathode ray tube (CRT) displays and been widely used in various electronic products, such as notebook computers, personal digital assistants (PDAs), flat panel TVs, or mobile phones. An LCD device display images by driving the pixels of the panel using source drivers and gate drivers. According to the driving modes, an LCD device may adopt a single-gate pixel structure or a double-gate pixel structure. The LCD device with double-gate pixel structure includes twice the number of gate lines and half the number of data lines, and thus requires more gate driving chips and fewer source driving chips when compared to the LCD device with single-gate pixel structure for the same resolution. Compared to a source driving chip, a gate driving chip is less expensive and consumes less power. Therefore, double-gate pixel structure can reduce manufacturing costs and power consumption.
FIGS. 1 and 2 are diagrams illustrating prior art double-gate LCD devices 100 and 200. The LCD devices 100 and 200 both include a timing controller 130, a source driver 110, a gate driver 120, a plurality of data lines DL1-DLm, and a plurality of gate lines GL1-GLn. The timing controller 130 can generate control signals for operating the source driver 110, such as a horizontal synchronization signal HSYNC, a horizontal start pulse signal STH, a scan sequence signal UPDN and an output enable signal OEH. According to the scan sequence signal UPDN, the source driver 110 can generate a vertical start pulse signal STVU or STVD, based on which the gate driver 120 controls the scan sequence of the gate lines GL1-GLn. For example, when the scan sequence signal UPDN is logic 0, the source driver 110 outputs the vertical start pulse signal STVU so that the gate driver 120 sequentially outputs the gate driving signals SG1-SGn, thereby scanning the gate lines GL1-GLn in an up-to-down direction; when the scan sequence signal UPDN is logic 1, the source driver 110 outputs the vertical start pulse signal STVD so that the gate driver 120 sequentially outputs the gate driving signals SGn-SG1, thereby scanning the gate lines GLn-GL1 in a down-to-up direction.
The LCD device 100 depicted in FIG. 1 further includes a pixel matrix 140 having a plurality of pixel units PXu and PXD. Each pixel unit, including a thin film transistor switch TFT, a liquid crystal capacitor CLC and a storage capacitor CST, is coupled to a corresponding data line, a corresponding gate line and a common voltage VCOM. In the LCD device 100, the odd-numbered columns of the pixel units PXu are respectively coupled to the corresponding odd-numbered gate lines GL1, GL3, . . . , GLn-1, while the even-numbered columns of the pixel units PXD are respectively coupled to the corresponding even-numbered gate lines GL2, GL4, . . . , GLn (assuming n is a positive even number). The LCD device 200 depicted in FIG. 2 further includes a pixel matrix 240 having a plurality of pixel units PXu and PXD. Each pixel unit, including a thin film transistor switch TFT, a liquid crystal capacitor CLC and a storage capacitor CST, is coupled to a corresponding data line, a corresponding gate line and a common voltage VCOM. In the LCD device 200, the odd-numbered columns of the pixel units PXD are respectively coupled to the corresponding even-numbered gate lines GL2, GL4, . . . , GLn, while the even-numbered columns of the pixel units PXU are respectively coupled to the corresponding odd-numbered gate lines GL1, GL3, . . . , GLn-1 (assuming n is a positive even number).
Although the pixel matrices 140 and 240 have different layouts, the LCD devices 100 and 200 both adopt double-gate pixel structure in which two adjacent gate lines control a corresponding row of pixel units and each data line transmits data to two adjacent columns of pixel units. Since the source driver 110 may output odd-numbered or even-numbered data to a data line, two gate lines are used for controlling each row of pixel units, so that the odd-numbered column of pixel units can correctly receive the odd-numbered data and the even-numbered column of pixel units can correctly receive the even-numbered data. The prior art source driver 110 includes a data processor 114, an odd data latch 111, an even data latch 112, and a multiplexer circuit 116. The data processor 114 can receive an original image data DATA. The odd-numbered data and the even-numbered data can then be provided by latching the original image data DATA using the odd data latch 111 and the even data latch 112, respectively. The multiplexer circuit 116 can thus output the odd-numbered data or the even-numbered data according to the output enable signal OEH received from the timing controller 130. Since the double-gate pixel structure may include different pixel layouts, data error may occur in the LCD device 200 if the source driver 110 is designed according to the pixel matrix 140 of the LCD device 100. Likewise, data error may occur in the LCD device 100 if the source driver 110 is designed according to the pixel matrix 240 of the LCD device 200.
FIG. 3 is a timing diagram illustrating the operation of the LCD 200 when the source driver 110 is designed according to the pixel matrix 240 of the LCD device 200. The horizontal start pulse signal STH determines the scan start point of each gate line. The output enable signal OEH switches phase once during the scan period of each gate line. First, illustrations are made to the output sequence of the source driver 110 when the scan sequence signal UPDN is logic 0: when the output enable signal OEH is logic 0, the source driver 110 outputs the even-numbered data D2, D4, . . . , Dm; when the output enable signal OEH is logic 1, the source driver 110 outputs the odd-numbered data D1, D3, . . . , Dm-1. During this period (UPDN=0), the gate driver 120 sequentially scans the gate lines GL1-GLn: the even-numbered pixel unit PXu controlled by the gate line GL1 is first turned on, thereby correctly receiving the even-numbered data D2 transmitted from the data line DL1; the odd-numbered pixel unit PXD controlled by the gate line GL2 is then turned on, thereby correctly receiving the odd-numbered data D1 transmitted from the data line DL1; and so on so forth. However, if the timing diagram depicted in FIG. 3 is applied to the LCD device 100, the odd-numbered pixel unit PXu controlled by the gate line GL1 is first turned on, thereby incorrectly receiving the even-numbered data D2 transmitted from the data line DL1; the even-numbered pixel unit PXD controlled by the gate line GL2 is then turned on, thereby incorrectly receiving the odd-numbered data D1 transmitted from the data line DL1; and so on so forth.
similarly, illustrations are made to the output sequence of the source driver 110 when the scan sequence signal UPDN is logic 1: when the output enable signal OEH is logic 1, the source driver 110 outputs the odd-numbered data D1, D3, . . . , Dm-1; when the output enable signal OEH is logic 0, the source driver 110 outputs the even-numbered data D2, D4, . . . , Dm. During this period (UPDN=1), the gate driver 120 sequentially scans the gate lines GLn-GL1: the odd-numbered pixel unit PXD controlled by the gate line GLn is first turned on, thereby correctly receiving the odd-numbered data D1 transmitted from the data line DL1; the even-numbered pixel unit PXu controlled by the gate line GLn-1 is then turned on, thereby correctly receiving the even-numbered data D2 transmitted from the data line DL1; and so on so forth. However, if the timing diagram depicted in FIG. 3 is applied to the LCD device 100, the even-numbered pixel unit PXD controlled by the gate line GLn is first turned on, thereby incorrectly receiving the odd-numbered data D1 transmitted from the data line DL1; the odd-numbered pixel unit PXu controlled by the gate line GLn-1 is then turned on, thereby incorrectly receiving the even-numbered data D2 transmitted from the data line DL1; and so on so forth.
In the prior art double-gate LCD devices, an LCD panel having a specific pixel layout can only be correctly driven using a specific source driver. To avoid data error in other applications, either the pixel layout or the design of the source driver needs to be changed, which may increase manufacturing costs.